circuit AdderTestHarness :
  module Adder :
    input clock : Clock
    input reset : Reset
    output auto : { flip in_1 : UInt<4>, flip in_0 : UInt<4>, out : UInt<4>}

    clock is invalid
    reset is invalid
    auto is invalid
    wire bundleIn_0 : UInt<4> @[Nodes.scala 1210:84]
    bundleIn_0 is invalid @[Nodes.scala 1210:84]
    wire bundleIn_1 : UInt<4> @[Nodes.scala 1210:84]
    bundleIn_1 is invalid @[Nodes.scala 1210:84]
    wire bundleOut_0 : UInt<4> @[Nodes.scala 1207:84]
    bundleOut_0 is invalid @[Nodes.scala 1207:84]
    auto.out <= bundleOut_0 @[LazyModule.scala 311:12]
    bundleIn_0 <= auto.in_0 @[LazyModule.scala 309:16]
    bundleIn_1 <= auto.in_1 @[LazyModule.scala 309:16]
    node _bundleOut_0_T = add(bundleIn_0, bundleIn_1) @[diplomacy.scala 57:51]
    node _bundleOut_0_T_1 = tail(_bundleOut_0_T, 1) @[diplomacy.scala 57:51]
    bundleOut_0 <= _bundleOut_0_T_1 @[diplomacy.scala 57:22]

  module MaxPeriodFibonacciLFSR :
    input clock : Clock
    input reset : Reset
    output io : { flip seed : { valid : UInt<1>, bits : UInt<1>[4]}, flip increment : UInt<1>, out : UInt<1>[4]}

    wire _state_WIRE : UInt<1>[4] @[PRNG.scala 46:28]
    _state_WIRE[0] <= UInt<1>("h1") @[PRNG.scala 46:28]
    _state_WIRE[1] <= UInt<1>("h0") @[PRNG.scala 46:28]
    _state_WIRE[2] <= UInt<1>("h0") @[PRNG.scala 46:28]
    _state_WIRE[3] <= UInt<1>("h0") @[PRNG.scala 46:28]
    reg state : UInt<1>[4], clock with :
      reset => (reset, _state_WIRE) @[PRNG.scala 55:49]
    when io.increment : @[PRNG.scala 69:22]
      node _T = xor(state[3], state[2]) @[LFSR.scala 15:41]
      state[0] <= _T @[PRNG.scala 70:11]
      state[1] <= state[0] @[PRNG.scala 70:11]
      state[2] <= state[1] @[PRNG.scala 70:11]
      state[3] <= state[2] @[PRNG.scala 70:11]
    when io.seed.valid : @[PRNG.scala 73:22]
      state[0] <= io.seed.bits[0] @[PRNG.scala 74:11]
      state[1] <= io.seed.bits[1] @[PRNG.scala 74:11]
      state[2] <= io.seed.bits[2] @[PRNG.scala 74:11]
      state[3] <= io.seed.bits[3] @[PRNG.scala 74:11]
    io.out <= state @[PRNG.scala 78:10]

  module AdderDriver :
    input clock : Clock
    input reset : Reset
    output auto : { out_1 : UInt<4>, out_0 : UInt<4>}

    clock is invalid
    reset is invalid
    auto is invalid
    wire bundleOut_0 : UInt<4> @[Nodes.scala 1207:84]
    bundleOut_0 is invalid @[Nodes.scala 1207:84]
    wire bundleOut_1 : UInt<4> @[Nodes.scala 1207:84]
    bundleOut_1 is invalid @[Nodes.scala 1207:84]
    auto.out_0 <= bundleOut_0 @[LazyModule.scala 311:12]
    auto.out_1 <= bundleOut_1 @[LazyModule.scala 311:12]
    inst randomAddend_prng of MaxPeriodFibonacciLFSR @[PRNG.scala 91:22]
    randomAddend_prng.clock <= clock
    randomAddend_prng.reset <= reset
    randomAddend_prng.io.seed.valid <= UInt<1>("h0") @[PRNG.scala 92:24]
    randomAddend_prng.io.seed.bits[0] is invalid @[PRNG.scala 93:23]
    randomAddend_prng.io.seed.bits[1] is invalid @[PRNG.scala 93:23]
    randomAddend_prng.io.seed.bits[2] is invalid @[PRNG.scala 93:23]
    randomAddend_prng.io.seed.bits[3] is invalid @[PRNG.scala 93:23]
    randomAddend_prng.io.increment <= UInt<1>("h1") @[PRNG.scala 94:23]
    node randomAddend_lo = cat(randomAddend_prng.io.out[1], randomAddend_prng.io.out[0]) @[PRNG.scala 95:17]
    node randomAddend_hi = cat(randomAddend_prng.io.out[3], randomAddend_prng.io.out[2]) @[PRNG.scala 95:17]
    node randomAddend = cat(randomAddend_hi, randomAddend_lo) @[PRNG.scala 95:17]
    bundleOut_0 <= randomAddend @[diplomacy.scala 78:51]
    bundleOut_1 <= randomAddend @[diplomacy.scala 78:51]

  module MaxPeriodFibonacciLFSR_1 :
    input clock : Clock
    input reset : Reset
    output io : { flip seed : { valid : UInt<1>, bits : UInt<1>[4]}, flip increment : UInt<1>, out : UInt<1>[4]}

    wire _state_WIRE : UInt<1>[4] @[PRNG.scala 46:28]
    _state_WIRE[0] <= UInt<1>("h1") @[PRNG.scala 46:28]
    _state_WIRE[1] <= UInt<1>("h0") @[PRNG.scala 46:28]
    _state_WIRE[2] <= UInt<1>("h0") @[PRNG.scala 46:28]
    _state_WIRE[3] <= UInt<1>("h0") @[PRNG.scala 46:28]
    reg state : UInt<1>[4], clock with :
      reset => (reset, _state_WIRE) @[PRNG.scala 55:49]
    when io.increment : @[PRNG.scala 69:22]
      node _T = xor(state[3], state[2]) @[LFSR.scala 15:41]
      state[0] <= _T @[PRNG.scala 70:11]
      state[1] <= state[0] @[PRNG.scala 70:11]
      state[2] <= state[1] @[PRNG.scala 70:11]
      state[3] <= state[2] @[PRNG.scala 70:11]
    when io.seed.valid : @[PRNG.scala 73:22]
      state[0] <= io.seed.bits[0] @[PRNG.scala 74:11]
      state[1] <= io.seed.bits[1] @[PRNG.scala 74:11]
      state[2] <= io.seed.bits[2] @[PRNG.scala 74:11]
      state[3] <= io.seed.bits[3] @[PRNG.scala 74:11]
    io.out <= state @[PRNG.scala 78:10]

  module AdderDriver_1 :
    input clock : Clock
    input reset : Reset
    output auto : { out_1 : UInt<4>, out_0 : UInt<4>}

    clock is invalid
    reset is invalid
    auto is invalid
    wire bundleOut_0 : UInt<4> @[Nodes.scala 1207:84]
    bundleOut_0 is invalid @[Nodes.scala 1207:84]
    wire bundleOut_1 : UInt<4> @[Nodes.scala 1207:84]
    bundleOut_1 is invalid @[Nodes.scala 1207:84]
    auto.out_0 <= bundleOut_0 @[LazyModule.scala 311:12]
    auto.out_1 <= bundleOut_1 @[LazyModule.scala 311:12]
    inst randomAddend_prng of MaxPeriodFibonacciLFSR_1 @[PRNG.scala 91:22]
    randomAddend_prng.clock <= clock
    randomAddend_prng.reset <= reset
    randomAddend_prng.io.seed.valid <= UInt<1>("h0") @[PRNG.scala 92:24]
    randomAddend_prng.io.seed.bits[0] is invalid @[PRNG.scala 93:23]
    randomAddend_prng.io.seed.bits[1] is invalid @[PRNG.scala 93:23]
    randomAddend_prng.io.seed.bits[2] is invalid @[PRNG.scala 93:23]
    randomAddend_prng.io.seed.bits[3] is invalid @[PRNG.scala 93:23]
    randomAddend_prng.io.increment <= UInt<1>("h1") @[PRNG.scala 94:23]
    node randomAddend_lo = cat(randomAddend_prng.io.out[1], randomAddend_prng.io.out[0]) @[PRNG.scala 95:17]
    node randomAddend_hi = cat(randomAddend_prng.io.out[3], randomAddend_prng.io.out[2]) @[PRNG.scala 95:17]
    node randomAddend = cat(randomAddend_hi, randomAddend_lo) @[PRNG.scala 95:17]
    bundleOut_0 <= randomAddend @[diplomacy.scala 78:51]
    bundleOut_1 <= randomAddend @[diplomacy.scala 78:51]

  module AdderMonitor :
    input clock : Clock
    input reset : Reset
    output auto : { flip node_sum_in : UInt<4>, flip node_seq_in_1 : UInt<4>, flip node_seq_in_0 : UInt<4>}
    output io : { error : UInt<1>}

    clock is invalid
    reset is invalid
    auto is invalid
    io is invalid
    wire bundleIn_0 : UInt<4> @[Nodes.scala 1210:84]
    bundleIn_0 is invalid @[Nodes.scala 1210:84]
    wire bundleIn_0_1 : UInt<4> @[Nodes.scala 1210:84]
    bundleIn_0_1 is invalid @[Nodes.scala 1210:84]
    wire bundleIn_0_2 : UInt<4> @[Nodes.scala 1210:84]
    bundleIn_0_2 is invalid @[Nodes.scala 1210:84]
    bundleIn_0 <= auto.node_seq_in_0 @[LazyModule.scala 309:16]
    bundleIn_0_1 <= auto.node_seq_in_1 @[LazyModule.scala 309:16]
    bundleIn_0_2 <= auto.node_sum_in @[LazyModule.scala 309:16]
    node _T = asUInt(reset) @[diplomacy.scala 94:11]
    node _T_1 = eq(_T, UInt<1>("h0")) @[diplomacy.scala 94:11]
    when _T_1 : @[diplomacy.scala 94:11]
      printf(clock, UInt<1>("h1"), "%d + %d = %d", bundleIn_0, bundleIn_0_1, bundleIn_0_2) : printf @[diplomacy.scala 94:11]
    node _io_error_T = add(bundleIn_0, bundleIn_0_1) @[diplomacy.scala 97:75]
    node _io_error_T_1 = tail(_io_error_T, 1) @[diplomacy.scala 97:75]
    node _io_error_T_2 = neq(bundleIn_0_2, _io_error_T_1) @[diplomacy.scala 97:36]
    io.error <= _io_error_T_2 @[diplomacy.scala 97:14]

  module AdderTestHarness :
    input clock : Clock
    input reset : UInt<1>
    output auto : { }

    clock is invalid
    reset is invalid
    auto is invalid
    inst adder of Adder @[diplomacy.scala 106:25]
    adder.clock is invalid
    adder.reset is invalid
    adder.auto is invalid
    adder.clock <= clock
    adder.reset <= reset
    inst drivers of AdderDriver @[diplomacy.scala 108:51]
    drivers.clock is invalid
    drivers.reset is invalid
    drivers.auto is invalid
    drivers.clock <= clock
    drivers.reset <= reset
    inst drivers_1 of AdderDriver_1 @[diplomacy.scala 108:51]
    drivers_1.clock is invalid
    drivers_1.reset is invalid
    drivers_1.auto is invalid
    drivers_1.clock <= clock
    drivers_1.reset <= reset
    inst monitor of AdderMonitor @[diplomacy.scala 110:27]
    monitor.clock is invalid
    monitor.reset is invalid
    monitor.auto is invalid
    monitor.io is invalid
    monitor.clock <= clock
    monitor.reset <= reset
    monitor.auto.node_sum_in <= adder.auto.out @[LazyModule.scala 298:16]
    adder.auto.in_0 <= drivers.auto.out_0 @[LazyModule.scala 296:16]
    monitor.auto.node_seq_in_0 <= drivers.auto.out_1 @[LazyModule.scala 298:16]
    adder.auto.in_1 <= drivers_1.auto.out_0 @[LazyModule.scala 296:16]
    monitor.auto.node_seq_in_1 <= drivers_1.auto.out_1 @[LazyModule.scala 298:16]
    when monitor.io.error : @[diplomacy.scala 119:35]
      node _T = bits(reset, 0, 0) @[diplomacy.scala 120:13]
      node _T_1 = eq(_T, UInt<1>("h0")) @[diplomacy.scala 120:13]
      when _T_1 : @[diplomacy.scala 120:13]
        printf(clock, UInt<1>("h1"), "something went wrong") : printf @[diplomacy.scala 120:13]

